Key features
Python framework developed by Multifractal
Enables rapid OA RF PCELL development
Code in “1D wire-frame” mode – framework generates 3D
Generate complex structures with ~100 lines of code
DRC clean and process agnostic: rules loaded from tech file
Shortens development time from months to weeks
Si-proven in 28 CMOS - compatible with other processes - please inquire
Integrates with Synopsys PyCell, Cadence & Keysight ADS AEL design flows
Any conceivable, fully parameterized RF CMOS layout can be defined using high-level abstracts. The coder can think in 1D wire-frame mode and focus on the RF design problem at hand. The framework then generates 3D details in an optimal and consistent way.
Both simulation layouts (Keysight ADS) and tapeout layouts (Synopsys/Cadence) are generated from the same underlying code; but different simplifications are applied, as defined by the coder/RFCell user. This allows for accurate and consistent EM simulations and eliminates the need for export/import of layouts between EDA tools.
Tape-out mode
Simulation-mode
Generate RF PCELLS easily
Simulate & tapeout the same design
With less than 100 lines of code, complex fully parameterized structures such as the 2 layer transformer above are easily generated (it has many hidden features: in/out rotation, sandwiching of layers, etc.). That is: without the loss of design flexibility & generality.
All in Python
The RFCell framework reads in process tech files to generate DRC compliant, tapeout-ready structures. Although this does not completely alleviate the burden of DRC-aware design by the coder/user, it does make the task significantly easier allowing for more effort and focus to go into the RF design.
